VLSI & Physical Design
By Gursimran S · For more details: info@ondevtra.com
AI Silicon
From Transformer Math to Physical Silicon — Designing an LLM AI Accelerator
How LLM workloads translate into silicon: tensor compute architecture, prefill vs decode, routing congestion, IR drop, thermal hotspots, and physical design solutions.
Read Article🔌
VLSI Engineering
Power Grid Design: Meshes, Via Stacks, Rails & Level Shifters
How power physically reaches standard cells — from package bumps through upper-metal meshes, stacked vias, M1 rails, and dual-rail level shifters in multi-voltage SoCs.
Read Article⚡
VLSI Engineering
MCMM Timing Closure at Advanced Nodes
Strategies that actually work — OCV/AOCV/POCV derating, cross-corner CTS balancing, useful skew, ECO flows, and real WNS/TNS numbers from tapeouts.
Read Article🔋
VLSI Engineering
Low Power Design in VLSI — Challenges & Solutions
Power gating, UPF, multi-Vt optimization, clock gating, DVFS — practical techniques with real power reduction numbers from production tapeouts.
Read Article
