Static Timing Analysis (STA)

Introduction

Static Timing Analysis (STA) verifies timing without simulation vectors. Using cell models (Liberty .lib), parasitics (e.g., SPEF), and constraints (SDC), STA computes arrival vs required times for every path and reports slack. Negative slack means a violation.

Core timing concepts

• Arrival time (AT): when a signal reaches an endpoint.
• Required time (RT): the latest (setup) or earliest (hold) time allowed by clocking.
• Slack: RT − AT. Positive is good; negative is a violation.
• Setup vs Hold: Setup checks use max delays (slow corner). Hold checks use min delays (fast corner).
• Clock Latency & Skew: distribution delays directly impact slack; useful skew can help but must be controlled.

Constraints (SDC) quick start

SDC describes clocks, I/O relationships, and path exceptions. Keep it minimal and explicit.

# Create clocks
create_clock -name core_clk -period 5.000 [get_ports clk]  ;# 200 MHz

# Derivatives / generated clocks (example)
create_generated_clock -name mem_clk -divide_by 2 -source [get_ports clk] [get_pins u_div/Q]

# I/O timing (external device relative to core_clk)
set_input_delay  0.80 -clock core_clk [get_ports din*]
set_output_delay 0.90 -clock core_clk [get_ports dout*]

# Basic uncertainties
set_clock_uncertainty 0.10 [get_clocks core_clk]
set_clock_uncertainty 0.12 -setup  [get_clocks mem_clk]
set_clock_uncertainty 0.06 -hold   [get_clocks mem_clk]

# Exceptions
# set_false_path -from [get_clocks scan_clk]
# set_multicycle_path 2 -setup -from [get_ports slow_in*] -to [get_registers *acc*]
# set_multicycle_path 1 -hold  -from [get_ports slow_in*] -to [get_registers *acc*]

PVT & corners

Process, Voltage, and Temperature change cell & wire delays. Time your design at multiple corners to be safe:

• Slow corner (SS, Vmin, Tmax): worst for setup (max delays).
• Fast corner (FF, Vmax, Tmin): worst for hold (min delays).
• Typical (TT): sanity check.

OpenSTA evaluates min/max delays per Liberty. For more realism, advanced derates exist: OCV/AOCV/POCV (beyond this intro).

MCMM strategy (multi-corner, multi-mode)

1. Define modes: functional, scan, low-power, etc., each with its SDC.
2. Select corners: at least SS@Tmax for setup and FF@Tmin for hold; add TT for coverage.
3. Automate loops: for each (mode, corner) run OpenSTA, collect worst slacks (WNS/TNS) and track regressions.

OpenSTA flow & commands

Typical inputs: gate netlist (Verilog), Liberty (min/max), SDC, parasitics (SPEF) and optional DEF for mapping.

# Load libraries (min for hold, max for setup)
read_liberty -min sky130_fd_sc_hd__ff_1v95_0C.lib
read_liberty -max sky130_fd_sc_hd__ss_1v60_125C.lib

# Design
read_verilog build/counter_netlist.v
link_design counter

# Constraints
read_sdc constraints/core.sdc

# Parasitics (after route)
read_spef results/counter.spef

# Update & basic reports
update_timing
report_worst_slack -max
report_worst_slack -min
report_checks -path_delay max -fields {slew capacitance} -digits 3 -nworst 10 > reports/setup_top10.rpt
report_checks -path_delay min -fields {slew capacitance} -digits 3 -nworst 10 > reports/hold_top10.rpt

# Pseudocode: SS@Tmax for setup, FF@Tmin for hold
# set lib_max "sky130_fd_sc_hd__ss_1v60_125C.lib"
# set lib_min "sky130_fd_sc_hd__ff_1v95_0C.lib"
# foreach mode {func scan} {
#   read_sdc constraints/${mode}.sdc
#   read_liberty -max $lib_max
#   read_liberty -min $lib_min
#   update_timing
#   report_worst_slack -max > reports/${mode}_wns_setup.rpt
#   report_worst_slack -min > reports/${mode}_wns_hold.rpt
# }

Tip: after placement/route, timing depends strongly on parasitics — always re-run STA with read_spef.

I/O timing essentials

• set_input_delay / set_output_delay model the external device’s launch/capture timing relative to your clock.
• Board margins: include PCB delay, jitter, and clock uncertainty as budget.
• Asynchronous inputs: mark CDC paths with set_false_path and use synchronizers.

Closing timing: common fixes

• Setup (max) fixes: upsize cells, buffer long nets, pipeline (add registers), reduce logic depth, relax frequency.
• Hold (min) fixes: insert small delay buffers on offending paths, use lower-drive or higher-VT cells on short fast nets.
• Clock quality: reduce skew/jitter; revisit CTS targets; leverage useful skew carefully.
• Constraints hygiene: keep exceptions minimal; wrong false paths mask real problems.

Sign-off checklist

• All target modes analyzed (functional/scan/low-power…)
• All required corners analyzed (at least SS@Tmax + FF@Tmin + TT)
• Zero (or waived) setup/hold violations (WNS ≥ 0, TNS = 0)
• Parasitics included; clock uncertainty accounted; I/O timed
• Reports archived with tool/PDK versions for traceability

FAQ

Why do I still fail hold after fixing setup? Setup fixes often speed up paths (upsizing/buffering). Always re-check hold in the fast corner.

Do I need OCV? For tapeout-grade sign-off, yes (AOCV/POCV). For learning and open PDKs, min/max libraries with margin are a good start.