Introduction
Physical Design (PD) turns a hardware description (RTL) into a manufacturable layout (GDSII). For years, this required costly EDA software. Today, the open-source stack—Yosys (synthesis), OpenROAD (PD automation), Magic (layout/DRC), and OpenSTA (timing)—lets anyone learn end-to-end, for free.
Why learn physical design?
- High demand: chips power AI, mobile, automotive, and datacenter; PD skills are scarce.
- Hands-on learning: see how floorplanning, CTS, routing, and timing closure fit together.
- Open tapeouts: programs like Efabless & TinyTapeout make real silicon accessible.
VLSI flow at a glance
- RTL (Verilog) → functional simulation.
- Logic synthesis (Yosys) → gate-level netlist using a standard cell library.
- Floorplanning → die size, aspect ratio, IO/power planning.
- Placement → place cells; optimize congestion & timing.
- CTS → clock tree to balance skew/latency.
- Routing → connect with metal; fix DRC/timing.
- STA → verify setup/hold across corners (OpenSTA).
- DRC/LVS → rule checks & schematic equivalence (Magic/Netgen).
- Sign-off & GDSII → ready for fabrication.
Install the toolchain (Linux & Docker)
Ubuntu (22.04+) is the smoothest path. Docker gives you a reproducible environment.
# Update & essentials
sudo apt update && sudo apt -y upgrade
sudo apt -y install build-essential git cmake python3
# Install open-source EDA tools
sudo apt -y install yosys openroad magic klayout iverilog gtkwave netgen
# Optional: OpenSTA from source (if repo pkg not available)
git clone https://github.com/The-OpenROAD-Project/OpenSTA.git
cd OpenSTA && mkdir build && cd build && cmake .. && make -j$(nproc) && sudo make install
# Get the official OpenROAD flow container
docker pull openroad/flow
docker run -it --name or_flow -v $PWD:/work -w /work openroad/flow bash
Tip: If package versions are older on your distro, prefer Docker or build from source to match tutorials.
PDK & libraries (SkyWater & friends)
Tools alone aren’t enough: you need a PDK (process design kit) and a standard cell library. The most popular open PDK is SkyWater 130 nm (sky130). It includes LEF/Liberty views, DRC/LVS rules, and cells.
git clone https://github.com/google/skywater-pdk.git
# Many flows fetch pre-packaged sky130 for you; check your flow's README.
Your first RTL → GDS: 4-bit counter
We’ll write a tiny design, synthesize it, place & route, then inspect layout.
1) Write RTL
module counter #(parameter N=4) (input clk, rst, output reg [N-1:0] q);
always @(posedge clk or posedge rst) begin
if (rst) q <= 0;
else q <= q + 1'b1;
end
endmodule2) Synthesize with Yosys
# Point to your Liberty file from the sky130 standard cell library
read_verilog counter.v
synth -top counter
dfflibmap -liberty sky130_fd_sc_hd__tt_025C_1v80.lib
abc -liberty sky130_fd_sc_hd__tt_025C_1v80.lib
write_verilog counter_netlist.v
3) Floorplan, place & route (OpenROAD)
read_liberty sky130_fd_sc_hd__tt_025C_1v80.lib
read_lef sky130_fd_sc_hd.tlef
read_lef sky130_fd_sc_hd__merged.lef
read_verilog counter_netlist.v
link_design counter
initialize_floorplan -utilization 0.45 -core_space 2
place_design
cts
route_design
write_def counter.def
write_gds counter.gds
write_sdc counter.sdc
4) View & check in Magic
magic -T sky130A.tech
# In Magic console:
gds read counter.gds
load counter
drc check
Deep dive: core stages
Floorplanning
- Choose aspect ratio, set utilization targets (e.g., 40–60%).
- IO ring & power grid planning (straps, rings).
- Keep-out regions for macros; plan routing channels.
Placement & optimization
- Global → detailed placement; fix congestion hotspots.
- Timing-driven moves to reduce negative slack (WNS/TNS).
CTS (Clock Tree Synthesis)
- Goals: low skew, reasonable insertion delay.
- Common topologies: H-tree, balanced clustering.
Routing
- Preferred directions per metal layer; avoid jogs where possible.
- Iterate with STA to fix violations (buffering, sizing, detours).
Static Timing Analysis (OpenSTA)
STA validates setup and hold timing across process, voltage, and temperature (PVT) corners.
read_liberty sky130_fd_sc_hd__tt_025C_1v80.lib
read_verilog counter_netlist.v
read_sdc counter.sdc
link_design counter
report_checks -path_delay min_max -fields {slew capacitance} -digits 3
Tip: Practice MCMM (multi-corner, multi-mode) early—timing closure spans corners and modes.
DRC/LVS verification
- DRC (design rule check): layer widths/spacings, antenna, via rules.
- LVS (layout vs schematic): ensure layout connectivity matches netlist.
netgen -batch lvs "counter.spice counter" "counter_netlist.v counter" sky130A_setup.tcl lvs.log
Practice projects (in rising difficulty)
- 4-bit counter → learn the flow.
- Parameterized ALU (8/16-bit) → datapath timing.
- UART → IO placement & async boundaries.
- RISC-V Pico core → hierarchical floorplan, CTS challenges.
Best practices
- Use Docker for reproducible toolchains.
- Version everything: scripts, constraints (SDC), and logs.
- Constrain early: realistic clocks, IO delays, false/multicycle paths.
- Fix violations where they occur (don’t “over-buffer” globally).
- Iterate: PPA is a trade-off—Power, Performance, Area.
Glossary
- PDK: Process Design Kit—rules & models for a technology node.
- LEF/DEF: Abstract layout formats (cells/chip).
- Liberty (.lib): Timing/power models for standard cells.
- SDC: Synopsys Design Constraints—clocks, IO constraints.
- WNS/TNS: Worst-/Total-Negative Slack (timing quality).
Conclusion & next steps
With the open stack, you can practice real PD at home: write RTL, synthesize, place/route, and sign-off checks. Grow from small blocks to CPUs, then join community tapeouts. Keep notes, automate scripts, and track PPA metrics—this mirrors industry workflows.
Further reading: “CMOS VLSI Design” (Weste & Harris) for CMOS/physical foundations, and “The Art of Timing Closure” (Golshan) for STA/closure depth.
FAQ
Which OS is best? Ubuntu LTS (22.04+) or Docker on macOS/Linux.
Which PDK should I use? Start with SkyWater sky130; it’s beginner-friendly and widely supported.
How long to finish a first flow? A small counter can run RTL→GDS in under an hour once tools are set.
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