Complete RTL-to-GDSII physical design expertise — from logic synthesis through floorplanning, placement, CTS, routing, and tapeout signoff. Full MCMM (Multi-Corner Multi-Mode) optimization across the entire flow for timing closure at advanced process nodes.
The complete physical design flow carried out with MCMM constraints at every stage — from RTL handoff to final GDSII tapeout.
RTL is synthesized into a gate-level netlist targeting the technology library. Timing constraints (SDC), area targets, and power budgets are applied. Multi-mode constraints ensure the design meets requirements across all functional modes from the start.
Die size estimation, macro placement, IO ring planning, and power grid design. Power domain partitioning for multi-voltage designs with UPF. The power network is analyzed for IR drop across all MCMM scenarios to ensure reliable power delivery.
Standard cells are placed with timing-driven and congestion-aware algorithms. MCMM placement optimization simultaneously targets worst-case setup (slow corner) and hold (fast corner) paths. Cell sizing, buffer insertion, and logic restructuring are performed across all scenarios.
Clock trees are built to meet skew, latency, and transition targets across all MCMM corners. Multi-source CTS for complex clock architectures. Clock tree optimization accounts for OCV (On-Chip Variation) and ensures balanced insertion delay across process corners.
Global and detail routing with DRC-clean targets. Signal integrity analysis for crosstalk (SI), electromigration (EM), and antenna effects. Post-route timing optimization with MCMM ensures timing closure across all corners and modes simultaneously.
Full-chip STA across all MCMM scenarios — setup analysis at worst-case slow corners, hold analysis at best-case fast corners. CPPR, OCV/AOCV/POCV derating applied. Multi-mode analysis covers functional, test, and low-power modes simultaneously.
DRC (Design Rule Check), LVS (Layout vs. Schematic), ERC, and antenna checks. Final signoff STA with extracted parasitics (SPEF). IR drop signoff, EM signoff, and formal equivalence checking before GDSII tapeout.
The entire RTL-to-GDSII flow is carried out under MCMM constraints — simultaneously optimizing across multiple PVT corners and functional modes for robust timing closure.
Multi-Corner Multi-Mode (MCMM) is the industry-standard methodology for timing closure. Instead of optimizing one scenario at a time, MCMM simultaneously considers all PVT (Process, Voltage, Temperature) corners and all functional modes — ensuring the design works correctly under every operating condition in silicon.
Timing analysis and optimization across all PVT corners simultaneously — slow-slow (worst setup), fast-fast (worst hold), and nominal. Covers process variation, voltage droop, and temperature extremes.
Different functional modes have different active clock domains, timing constraints, and critical paths. MCMM handles all modes concurrently — functional, test/scan, JTAG, low-power sleep/retention modes.
MCMM is not just an STA technique — it's applied at every stage. Placement considers all scenarios, CTS balances across corners, routing optimizes for all modes, and signoff verifies every combination.
On-Chip Variation modeling with AOCV (Advanced OCV) and POCV (Parametric OCV) for realistic timing margins. Path-based and stage-based derating for accurate pessimism reduction at advanced nodes.
Hands-on experience with leading EDA tools from Synopsys and Cadence for the complete RTL-to-GDSII flow.
Deep expertise across the full spectrum of VLSI physical design challenges.
Looking for VLSI physical design expertise? Whether it's a full RTL-to-GDSII project or specific PD challenges — let's talk.
Available for contract, consulting, and full-time roles · info@ondevtra.com