Open-Source Physical Design

Learn VLSI Physical Design from Scratch — Free Open-Source Tools

Join our 12-week hands-on training program and build silicon-ready layouts using Yosys, OpenROAD, Magic, and OpenSTA — no commercial licenses or prior experience required.

OpenROAD Yosys Sky130 Tapeout skills
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No prior experience needed · Next batch starting soon · Limited seats per cohort

Engineers using neon dashboards to build VLSI layouts

What you master in 12 weeks

Every milestone reinforces real backend flow tasks with reproducible open-source labs.

RTL

RTL to netlist

Build clean synthesis scripts, constraint files, and QoR dashboards with Yosys + OpenSTA.

  • Clock/reset design patterns
  • Static timing checks at multiple corners
  • Power/performance/area trade studies
🧭

Physical planning

Floorplan, macro placement, power grid, and IO plans with automated validation.

  • Die/area estimation frameworks
  • Macro soft/hard constraints
  • IR drop + EM sanity checks
⚙️

Implementation flow

Placement, CTS, routing, and signoff steps scripted with OpenROAD and Magic.

  • Clock tree balancing and skew tuning
  • Route optimisation & ECO loops
  • Automated DRC/LVS pipelines
💼

Career readiness

Portfolio projects, resume boosters, and interview prep tailored to backend roles.

  • Report dashboards & design notebooks
  • Mock interviews & salary benchmarks
  • Hiring partner introductions

12-week roadmap

  • 01Week 1-2 — Linux lab setup, GitOps pipeline, RTL hygiene, constraint writing.
  • 02Week 3-4 — Synthesis experiments, timing audit, design exploration notebooks.
  • 03Week 5-6 — Floorplan automation, macro placement, PDN creation, IO planning.
  • 04Week 7-8 — Global/detailed placement, CTS, clock closure, incremental STA.
  • 05Week 9-10 — Routing strategies, congestion fixes, antenna & DRC closure.
  • 06Week 11-12 — Signoff verification, GDS export, portfolio polishing, interview prep.
Timeline showing six sprints of the VLSI physical design roadmap

Toolchain & automation coverage

Every module ships with Makefiles, Docker images, and CI pipelines so you can reproduce results anywhere.

Engineers collaborating on open-source EDA lab

Lab automation

Single command setup with Docker, Sky130 PDK, and reusable TCL scripts.

  • Yosys, OpenROAD, Magic, OpenSTA, Netgen.
  • Continuous integration on GitHub Actions.
  • Notebook-style reporting + Jupyter dashboards.
Designer reviewing signoff dashboards on neon monitors

Signoff readiness

Scripts to compare PPA, run ECO loops, and generate job-ready documentation.

  • Automated DRC/LVS, timing, and power checks.
  • Report diffing for ECO cycles and optimizations.
  • Portfolio templates for recruiters and managers.

Resources you get access to

  • LabsDownloadable open-source labs with Makefiles, TCL, and runbooks for each step.
  • TemplatesResume bullets, interview question banks, and design review slide decks.
  • CommunityPrivate Slack group, office hours, and peer review sessions.
  • HiringIntroductions to partner fabs, startups, and automotive semiconductor teams.
  • Interactive LabsPractice OpenROAD in your browser with AI-guided labs. Try the Platform →
Community of engineers reviewing VLSI projects

Ready to accelerate your VLSI career?

Share your background and goals—we’ll recommend the right roadmap, labs, and milestones for you.

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Free introductory session · Personalised learning plan · No obligation to enroll.

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