Backend VLSI Physical Design Training - 3 Months

Introduction

Backend Physical Design (PD) turns a verified RTL netlist into a manufacturable layout (GDSII). Our 3-month program is tightly scoped: you’ll learn the canonical flow—synthesis, floorplanning, placement, CTS, routing, STA, DRC/LVS, sign-off—entirely with free, open-source tools. You’ll script each step, keep reports, and understand how Power/Performance/Area (PPA) trade-offs are made.

Who is this for?

• CS/EE students and junior engineers who know basic Verilog and Linux shell.
• Embedded/FPGA folks wanting to cross over to ASIC backend.
• Anyone who prefers a practical, reproducible path to industry workflows.

Toolchain & labs (open-source)

We build a reproducible Linux/Docker lab so everyone sees the same results:

# Essentials
sudo apt update && sudo apt -y install build-essential git cmake python3

# Core tools
sudo apt -y install yosys magic klayout iverilog gtkwave netgen

# OpenROAD & OpenSTA (via container is easiest)
docker pull openroad/flow
docker run -it --name or_flow -v $PWD:/work -w /work openroad/flow bash

We use SkyWater sky130 PDK for libraries, tech files, and DRC/LVS rules.

12-week roadmap (3 months)

1. Week 1–2: RTL review, functional sim, Yosys synthesis, Liberty basics.
2. Week 3: Floorplanning—die/core, aspect ratio, IO & power grid, utilization.
3. Week 4–5: Placement—global/detailed, congestion fixes, timing-driven moves.
4. Week 6: CTS—skew vs insertion delay, H-trees, useful skew.
5. Week 7–8: Routing—DRC-clean routes, shielding, antenna fixes.
6. Week 9: STA—setup/hold, corners, SDCs, MCMM mindset.
7. Week 10: DRC/LVS—Magic & Netgen sign-off checks.
8. Week 11–12: Capstone: block-level tapeout-style run, reports & presentation.

Hands-on exercises

• 4-bit counter (first full flow, RTL→GDS).
• ALU (8/16-bit) with timing targets; placement & buffering practice.
• UART—IO placement, parasitics awareness, clock domain clean-ups.
• PPA challenges—hit area and frequency targets without breaking DRC/LVS.

Capstone projects

Choose one based on your comfort and ambitions:

1. Mini RISC-V core (hierarchical floorplan, tougher CTS/routing).
2. Streaming DSP block (pipelining for timing; low-congestion placement).
3. Peripheral subsystem (UART/SPI timers, top-level floorplan & power grid).

Careers & salaries

Titles you’ll target: Physical Design Engineer, STA Engineer, ASIC Backend Engineer. Compensation varies widely by region, company stage, and experience. As a broad orientation:

• Entry (0–2 yrs): typically starts at a competitive graduate-engineer package.
• Mid (3–6 yrs): meaningful jump as you own blocks & timing closure.
• Senior (7+ yrs): higher range—architecture input, sign-off responsibility.

These are indicative ranges, not offers—always research your local market.

How we teach

• Do-first labs with verified scripts and golden logs.
• Reviews on PPA trade-offs and failure analysis.
• Portfolio-ready artifacts: reports, screenshots, constraint files.
• Interview prep: whiteboard timing, floorplan scenarios, common CTS questions.

FAQ

Prerequisites? Comfortable with Verilog basics and Linux shell. We’ll guide the rest.

Hardware? Any modern laptop. Docker recommended for reproducibility.

Certificate? Yes—issued on capstone completion with rubric-based evaluation.

Placement help? CV feedback, mock rounds, and referral tips.

Apply / Contact

Ready to start? Email hello@ondevtra.com with the subject “VLSI PD Training”. We’ll reply with dates, pricing, and a short readiness checklist.